library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
library altera;
use altera.altera_primitives_components.all;

entity reg50bit is
	port(clock,write_en,read_en,shift,reset : in std_logic;
		data_search : in std_logic_vector(0 to 47);
		data_write, data_inshift : in std_logic_vector(0 to 49);
		data_outshift : out std_logic_vector(0 to 49);
		data_read : out std_logic_vector(48 to 49);
		data_found: out std_logic);
end reg50bit;

architecture struct of reg50bit is
	
	component mux50bit is
		port(a,b:	in std_logic_vector(0 to 49);
		s:	in std_logic;
		muxout:	out std_logic_vector(0 to 49));
	end component;
	
	signal input: std_logic_vector(0 to 49);
	signal intQ: std_logic_vector(0 to 49);
	signal s: std_logic_vector(0 to 47);
begin
mux: mux50bit port map(a=>data_write, b=>data_inshift, s=>shift, muxout=>input);

dff_array:
	for i in 0 to 49 generate
		d: dffe port map(prn=>'1',clrn=>not reset,ena=>(write_en xor shift),clk=>clock,d=>input(i),q=>intQ(i));
	end generate;

output_array:
	for k in 48 to 49 generate
		t: tri port map(a_in=>intQ(k),oe=>read_en,a_out=>data_read(k));
	end generate;

data_outshift <= intQ;
s <= data_search xnor intQ(0 to 47);
data_found <= s(0) and s(1) and s(2) and s(3) and s(4) and s(5) and s(6) and  s(7) and s(8) and s(9) and
			 s(10) and s(11) and s(12) and s(13) and s(14) and s(15) and s(16) and s(17) and s(18) and s(19) and
			 s(20) and s(21) and s(22) and s(23) and s(24) and s(25) and s(26) and s(27) and s(28) and s(29) and
			 s(30) and s(31) and s(32) and s(33) and s(34) and s(35) and s(36) and s(37) and s(38) and s(39) and
			 s(40) and s(41) and s(42) and s(43) and s(44) and s(45) and s(46) and s(47);
end struct;